1. Field of the Invention
This process relates generally to the fabrication of integrated circuits. In particular, a process for making metal contacts self-aligned to interconnecting metallurgy is described.
2. Background of the Invention
As manufacturers reduce the dimensions of integrated circuits, it is readily apparent that one of the greatest barriers to achieving sub-micron geometries is the area allotted to alignment or overlay tolerances which are required to assure adequate connections between metal contacts to the semiconductor devices themselves and the interconnecting metallurgy. An alignment or overlay tolerance allows for small errors in the alignment of photomasks used for patterning various layers without compromising the adequacy of the connections between the layers.
To better appreciate the problems encountered, as example of a prior art metal line and contact structure is shown in FIG. 1. As conventionally done in semiconductor processing, the contacts 10 to the semiconductor devices are first formed, and then in subsequent processing steps, the interconnecting metallurgy 12 is deposited. With the current limitations of conventional optical lithography tools, which have a standard overlay error of approximately 0.45 microns, in order to ensure that one micron wide lines 12 completely overlay the contacts 10, it is necessary that the contacts have a width of approximately 2 microns. Obviously, if one could eliminate the extra one micron border on the contact, as shown in FIG. 2, the ability to increase the maximum wiring density of metal lines 12 would be greatly improved.